The present invention relates to an image display apparatus and a driving method thereof, and particularly to an image display apparatus and a driving method thereof which are suitable for displaying an image according to a multi-tone digital signal.
Conventionally, there is known the following image display apparatus. A plurality of signal lines and a plurality of scanning lines are arranged in a matrix shape in a display region for displaying an image. The pixels connected to the signal lines and the scanning lines through the switch elements are provided in the respective regions near the intersections of the signal lines and the scanning lines. The scanning circuit for driving the scanning lines and the driving circuit for driving the signal lines are provided in the non-display region. The driving circuit is constructed to receive a six-bit 64-gradation digital signal and to generate a 64-gradation voltage according to this digital signal as disclosed in Extended Abstracts of the 1997 International Conference on Solid State Devices and Materials, pp.348-349, FIG. 2n, for example.
More specifically, this driving circuit includes a shift register, a data bus, two latches, and a DA converter circuit. That is, the data bus for transferring the six-bit binary data is provided between the shift register and one of the latches, which is connected to the data bus. In this case, the latch for driving one signal line has six signal paths which have their input sides connected to the respective lines of the data bus. In other words, the data bus and the one latch are connected through six lines. The 6-bit binary data fed on the six lines of the data bus are stored in the one latch in response to the latch pulse produced from the shift register. After the latch is all filled with the data, the data stored in the one latch is transferred in response to the latch pulse to the other latch, where it is stored. The data stored in the other latch is held until data is again latched. The data stored in the other latch is converted in the DA converter into one of the 64 different gradation voltages. The converted gradation voltage is produced on the signal line.
When the driving circuit is incorporated in the image display apparatus, the increase of the display gradation number of the image display apparatus (namely, the bit number of data) will result in the expansion of the region in which the driving circuit is formed in accordance with the increase of the number of the data lines. The increase of the region in which the driving circuit is formed in accordance with the increase of the display gradation number, however, results in the expansion of the non-display region. Thus, the area in which the driving circuit is formed must be limited. For example, in order to attain the image display apparatus having the definition of 200 pixels/inch with the pixels of the vertical color stripes, the interval of the signal lines is required to be 2.54 mm÷200÷3 (colors)≅42 μm. The circuit for driving one signal line must be disposed in this interval.
However, when the image display apparatus having the definition of 200 pixels/inch is tried to be constructed according to the conventional construction, the interval between the signal lines cannot be achieved as required because of the large number of the wiring lines.
That is, the prior image display apparatus is constructed in the following manner in order to transfer the 6-bit binary data to the DA converter. The data bus and the one latch are connected through the six lines, the one latch and the other latch are connected through the six lines, and the other latch and the DA converter are connected through the six lines. In addition, the image display apparatus uses two types of metals (namely, the gate metal used for the gate electrode of the thin film transistor (hereinafter, referred to as “TFT”) and the wiring metal connected to the source and drain electrodes of the TFT. It should be generally avoided to use three or more types of metals because of increasing the number of the processing steps, and hence the cost. Therefore, the six wiring lines (longitudinal lines) for connecting the data bus and the DA converter between which the two latches are provided, and the group of the lateral gradation voltage lines arranged to intersect the longitudinal lines at the DA converter are formed as two separate wiring layers. As a result, the six longitudinal lines cannot be overlapped each other, so that they are obliged to be formed in parallel. Accordingly, when the space and the wiring line are selected to be 4 μm and 4 μm according to the layout rule, the six wiring lines need the total width of (4+4)×6 (lines)=48 pm, which thus exceeds the required line width of 42 pm.
Moreover, the number of the TFTs is greatly affected by the increase of the gradation number. When the bit number of data is k, the DA converter alone needs the arrangement of the TFTs, the number of which is k×2k (e.g., 384 when k is 6). In addition, in order to provide two k-bit latches, it is necessary to use the layout rule of 1 pm or below, which is actually impractical.
Also, the power consumption of the driving circuit incorporated in the image display apparatus is required to be as small as possible. That is, the power consumption of the image display apparatus greatly affects the operating time of the battery-powered product with this display apparatus used. The data bus consumes power as a part of the power consumption of the driving circuit. The data bus functions to transmit the input data from the outside to the latches. The data bus is one of the wiring lines having the fast data transmission rate and the large power consumption. The power consumption of this data bus is proportional to the wiring capacitance, the number of the data changes, and the square of the signal voltage. Therefore, the power consumption of the data bus can be effectively reduced by decreasing the wiring capacitance, the number of the data changes, and the signal voltage. The wiring intersection capacitance of the wiring capacitance of the data bus is the great part.
Here, it is assumed that “k” represents the number of the wiring lines of the data bus. (k−1) (five when six bits are used) intersections per signal line are necessary as the wiring intersections of the data buses in order for the data from the data bus to be taken out at the one latch as in the prior art. Regarding the number of the data changes (the number of times that data is changed from “0” to “1” or from “1” to “0”), when “k” is assumed to be the number of the wiring lines of the data bus, the average data changes per data is k/2 (3 when six bits are used), and the maximum number of the data changes is k (6 when six bits are used).